Field of the Invention
The current invention is related to a programmable linear algebraic solver for large sparse matrices based on a lower-upper triangular decomposition method to be used in a hardware computing environment. Furthermore, the present invention also relates to models for power system components and power systems.
Brief Description of the Prior Art
Currently, power flow computation for large power systems is time intensive. The calculations are non-linear in nature and lengthy iteration schemes are the currently preferred solution. This presents a problem as many assumptions and simplifications are required to solve the equations in a timely manner. In addition, expansion of the power grid, increasing necessity and complexity of contingency studies and introduction of economic analysis are demanding further computational burden. Traditional digital methods are too slow to solve the aforementioned demands quickly. This affects the security, reliability and market operation of power systems. Ideally a real-time computation tool is preferable, specifically in market activities and operation.
In power flow computations, sparse linear solvers are used to calculate the update vector for the Jacobian matrix at each iterative step during Newton-Raphson iteration for load flow solution. The bottleneck in Newton power flow iteration is the solution of a sparse system of linear equations, which is required for each iteration, and typically consumes 85% of the execution time in large-scale power systems [1]. In practice, many related load flow computations are performed as part of contingency analysis. These multiple load flow computations can easily be performed in parallel. It remains desirable to speed up the computation of an individual load flow computation. Typical power flow computation is performed using general-purpose personal computing platforms based on processors such as the Intel Pentium IV®. High performance uniprocessor sparse linear solvers on these platforms utilize only roughly 1-4% of the floating-point throughput. Attempts have also been made to increase performance through the use of cluster computing [1], however, due to the irregular data flow and small granularity of the problem these methods do not scale very well.
Analog computation provides a viable alternative to traditional approaches. Among the advantages over traditional digital methods are physically realizable solutions and faster computation times. In order to make the analog method a viable tool in power system analysis, accurate models of power system components are required. A reconfigurable transmission line model is considered for a specific analog computation method. Traditional digital methods are expensive and slow in comparison to analog computers. The power flow solution is obtained almost instantaneously regardless of the number of components in the network with analog circuits. Essentially computation time is independent of network size. Effectively the solution is obtained as quickly as the system stabilizes. Experimentation has shown the ability to calculate solutions even faster than real time. In prior research, simulation time for a two-machine system was typically 104 times shorter than the real time simulated phenomena [101]. This is achieved by modeling generator dynamics for the purpose of transient stability evaluation.
The modeling and design of analog components is one obstacle that must be overcome. The solutions will only be as accurate as the models and measurements will allow. Without clearly defined valid models for power system components, the analog computational method will never be realized. In addition, these models also must cater towards computational speed. Specifically, in power system operation, multiple runs and contingencies are required to be executed extremely quickly. A priority for these analog models is to yield valid solutions while allowing fast reconfigurability.
An efficient strategy for designing analog emulation engines for large scale power system computation may be provided through the use of Analog Behavioral Models (ABMs) of PSpice [201]. Emulation can be described as an act of a physical system imitating a real system. Emulation in this patent application, therefore, is the representation of physical characteristics of a real life object (power system) using an electric circuit equivalent. The representational relationship could be mathematical, scaled, or both. The circuit equivalent representation has within it the model of a real system as well as a method of its solution. The speed of computation is as quick as the response of the circuit itself, which could be real time, faster or slower than real time depending on the parameter settings. The solution is continuous in time and amplitude.
Simulation on the other hand is an attempt to predict/replicate aspects of the behavior of a real system by creating an approximate (mathematical) model of it. Computer modeling, for example by providing a special-purpose computer program, may do this. The program is composed of equations that describe the functional relationships within the real system. When the program is run, the resulting mathematical dynamics form an analog of the behavior of the real system with the results presented in the form of data.
The need to emulate/simulate large and complex mixed-signal systems has prompted the development of high-level circuit representations for analog components; ABMs serve this purpose. The interior of a behavioral model, however, is different in that it is implemented in terms of algebraic or differential equations rather than physical analog components. In order words, in a behavioral model, the focus is on the input/output relationship of the block. The fundamental advantage of the behavioral modeling technique in top-down designs is that the simulation can provide fast prediction of system performance. The approach helps to select proper architectures for circuit implementation and analyze tradeoffs at the early design stages. The transistor level simulation (bottom-up design), comparatively, can be very tedious and cumbersome especially for mixed-signal chips containing a large number of analog components. Under such circumstances, behavioral models enable designers to verify the complex system efficiently and result in fast system evaluation prior to embarking on full structural design and implementation.
Static load flow analysis, which is based on the power flow equations, is one method currently used by the industry. The problem is that suchanalyses solve using a sequential method, which makes the simulation process very slow in complex networks. The speed of the digital computer to solve for static load flow is greatly dependent on the size of the power system network. An alternative method to solve static load flow is using an analog computer to emulate the behavior of the power system, instead of using model equations to simulate the network.
In the past two decades, silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology has become a major technology for integrating VLSI systems using a low-supply voltage [301]. Along with the progress in the CMOS technology, CMOS devices have been scaled down continuously and the corresponding power consumption has also been decreased, which have triggered advances in the circuit design techniques for various designs and applications. The association between CMOS circuits and VLSI chips is becoming increasingly easier to implement.
With these advances, Fried et al. [302], proposed an approach using an analog VLSI chip for simulation of the behavior of power systems. Using an analog VLSI chip can be limited if the fabricated chip is only useful for one power system configuration. Gu et al. [303], presented a concept to add reconfigurable parameters using switches and analog voltages to change the system configuration and parameters.